Solution
Software-Defined Radio Research
Wideband capture and playback with the FPGA source open to you, so the interesting work happens in your algorithm instead of in the plumbing.
Commercial SDR platforms hand you a fixed processing chain and a USB port. That is fine until the experiment needs more instantaneous bandwidth than the link can carry, or needs a block of processing to run before the data leaves the FPGA.
Our carriers give you the raw converter stream, a large FPGA with the link layer already built, and the room to put your own logic in the application layer. Digital down-conversion, filtering and channelization are available as ready blocks if you want them and removable if you do not.
Signal chain
Where our hardware sits
Highlighted stages are the ones we supply.
- 01 Antenna / RF front end your hardware
- 02 ADC or transceiver module FMC / FMC+
- 03 FPGA carrier PCIe or embedded
- 04 Host application Windows / Linux
Where to start
Products for this application
When instantaneous bandwidth is the binding constraint: 6.4 GSPS on one channel, or 3.2 GSPS on two.
Full-duplex experiments: 1 GSPS capture and 12 GSPS playback on one FMC site.
The usual lab host: half-length PCIe, up to 3.6 GB/s straight into host memory.
When the processing has to stay embedded, with four mSATA slots for local capture.
Before you specify
Questions worth settling early
- How much can actually reach the host?
- A PCIe Gen3 x8 carrier sustains about 3.6 GB/s. Two 1 GSPS 16-bit channels produce 4 GB/s, so beyond roughly one gigasample per second per channel you are either decimating, channelizing in the FPGA, or recording locally.
- Can we run our own FPGA code?
- Yes. The framework is layered, and the application layer is yours. The link and transport layers - PCIe, DDR, buffering, firmware management - stay ours so you are not rebuilding infrastructure to get to your algorithm.
- What about multi-channel phase coherence?
- Every converter module accepts an external clock and external trigger, and carriers accept a 10 MHz or 100 MHz reference plus IRIG-B. Channel-to-channel calibration is one of the standard FPGA blocks.
Send the bandwidth, channel count and run length. Typical response within one business day.
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